Cyclone V Device Datasheet
CV-51002 | 2018.05.07
DSP Block Performance Specifications
Table 32.
DSP Block Performance Specifications for Cyclone V Devices
Mode
Performance
–C7, –I7
300
Unit
–C6
340
287
287
250
310
310
310
310
310
–C8, –A7
Modes using One DSP Block
Independent 9 × 9 multiplication
260
200
200
160
200
200
200
200
200
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Independent 18 × 19 multiplication
Independent 18 × 18 multiplication
Independent 27 × 27 multiplication
Independent 18 × 25 multiplication
Independent 20 × 24 multiplication
Two 18 × 19 multiplier adder mode
18 × 18 multiplier added summed with 36-bit input
Complex 18 × 19 multiplication
250
250
200
250
250
250
250
Modes using Two DSP Blocks
250
Memory Block Performance Specifications
To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from
an on-chip PLL and set to 50% output duty cycle. Use the Intel Quartus Prime software to report timing for the memory block
clocking schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX
.
Table 33.
Memory Block Performance Specifications for Cyclone V Devices
Memory
Mode
Resources Used
Performance
–C7, –I7
350
Unit
ALUTs
Memory
–C6
420
420
340
–C8, –A7
300
MLAB
Single port, all supported widths
0
0
0
1
1
1
MHz
MHz
MHz
Simple dual-port, all supported widths
350
300
Simple dual-port with read and write at the same
address
290
240
continued...
Cyclone V Device Datasheet
44
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