Cyclone V Device Datasheet
CV-51002 | 2018.05.07
Symbol
Parameter
Condition
–C8, –A7 speed grades
—
Min
600
40
Typ
—
Max
1300
60
Unit
MHz
%
tEINDUTY
Input clock or external feedback clock input
duty cycle
—
fOUT
Output frequency for internal global or
regional clock
–C6, –C7, –I7 speed
grades
—
—
550(54)
MHz
–C8, –A7 speed grades
—
—
—
—
460(54)
667(54)
MHz
MHz
fOUT_EXT
Output frequency for external clock output
–C6, –C7, –I7 speed
grades
–C8, –A7 speed grades
—
—
—
533(54)
55
MHz
%
tOUTDUTY
Duty cycle for external clock output (when set
to 50%)
45
50
tFCOMP
External feedback clock compensation time
—
—
—
—
—
—
10
ns
tDYCONFIGCLK
100
MHz
Dynamic configuration clock for mgmt_clk
and scanclk
tLOCK
Time required to lock from end-of-device
configuration or deassertion of areset
—
—
—
—
—
—
1
1
ms
ms
tDLOCK
Time required to lock dynamically (after
switchover or reconfiguring any non-post-
scale counters/delays)
fCLBW
tPLL_PSERR
(53)
PLL closed-loop bandwidth
Low
Medium
High(55)
—
—
—
—
—
0.3
1.5
4
—
—
MHz
MHz
MHz
—
Accuracy of PLL phase shift
—
±50
ps
continued...
The VCO frequency reported by the Intel Quartus Prime software takes into consideration the VCO post-scale counter K value.
Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification.
(54)
(55)
This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL.
High bandwidth PLL settings are not supported in external feedback mode.
Cyclone V Device Datasheet
41
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