Cyclone V Device Datasheet
CV-51002 | 2018.05.07
High-Speed I/O Specifications
Table 34.
High-Speed I/O Specifications for Cyclone V Devices
When J = 1 or 2, bypass the serializer/deserializer (SERDES) block.
For LVDS applications, you must use the PLLs in integer PLL mode. This is achieved by using the LVDS clock network.
The Cyclone V devices support the following output standards using true LVDS output buffer types on all I/O banks.
•
•
True RSDS output standard with data rates of up to 360 Mbps
True mini-LVDS output standard with data rates of up to 400 Mbps
Symbol
Condition
–C6
Typ
—
–C7, –I7
Typ
–C8, –A7
Typ
Unit
MHz
MHz
Min
Max
Min
Max
Min
Max
fHSCLK_in (input clock frequency) True Differential I/O
Standards
Clock boost
factor W = 1 to
40(63)
5
437.5
5
—
420
5
—
320
fHSCLK_in (input clock frequency) Single-Ended I/O
Standards
Clock boost
factor W = 1 to
40(63)
5
—
320
5
—
320
5
—
275
fHSCLK_OUT (output clock frequency)
—
5
—
—
420
840
5
—
—
370
740
5
—
—
320
640
MHz
(65)
(65)
(65)
Transmitter
True Differential I/O Standards -
fHSDR (data rate)
SERDES factor J
=4 to 10(64)
Mbps
continued...
(63)
(64)
Clock boost factor (W) is the ratio between the input data rate and the input clock rate.
The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain
which is design dependent and requires timing analysis.
(65)
The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global,
regional, or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
Cyclone V Device Datasheet
46
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