Cyclone V Device Datasheet
CV-51002 | 2018.05.07
Symbol
Parameter
Condition
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
—
Min
—
Typ
—
Max
65
Unit
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
ps (p-p)
mUI (p-p)
%
(58)(60)
tOUTCCJ_IO
Cycle-to-cycle jitter for clock output on
regular I/O in integer PLL
—
—
650
65
—
—
(58)(60)(61)
tFOUTCCJ_IO
Cycle-to-cycle jitter for clock output on
regular I/O in fractional PLL
—
—
650
65
—
—
(58)(62)
tCASC_OUTPJ_DC
Period jitter for dedicated clock output in
cascaded PLLs
—
—
300
30
—
—
tDRIFT
—
—
±10
Frequency drift after PFDENA is disabled for a
duration of 100 µs
dKBIT
kVALUE
fRES
Bit number of Delta Sigma Modulator (DSM)
Numerator of fraction
—
—
8
24
32
Bits
—
128
8388608
5.96
2147483648
0.023
Resolution of VCO frequency
fINPFD = 100 MHz
390625
Hz
Related Information
Memory Output Clock Jitter Specifications on page 49
Provides more information about the external memory interface clock output jitter specifications.
(61)
(62)
This specification only covers fractional PLL for low bandwidth. The fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz.
The cascaded PLL specification is only applicable with the following conditions:
• Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz
• Downstream PLL: Downstream PLL BW > 2 MHz
Cyclone V Device Datasheet
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