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5CSEMA5F31C8N 参数 Datasheet PDF下载

5CSEMA5F31C8N图片预览
型号: 5CSEMA5F31C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 85000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 93 页 / 999 K
品牌: INTEL [ INTEL ]
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Cyclone V Device Datasheet  
CV-51002 | 2018.05.07  
Symbol  
Condition  
–C6  
Typ  
–C7, –I7  
Typ  
–C8, –A7  
Typ  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Emulated  
Differential I/O  
Standards  
tRISE and tFALL  
True Differential  
I/O Standards  
200  
250  
200  
250  
200  
300  
ps  
ps  
Emulated  
Differential I/O  
Standards with  
Three External  
Output Resistor  
Networks  
Emulated  
Differential I/O  
Standards with  
One External  
Output Resistor  
Network  
300  
300  
300  
ps  
TCCS  
True Differential  
I/O Standards  
200  
300  
250  
300  
250  
300  
ps  
ps  
Emulated  
Differential I/O  
Standards with  
Three External  
Output Resistor  
Networks  
Emulated  
Differential I/O  
Standards with  
One External  
Output Resistor  
Network  
300  
300  
300  
ps  
(65)  
(65)  
(65)  
(65)  
(65)  
(65)  
Receiver  
fHSDR (data rate)  
SERDES factor J  
=4 to 10(64)  
875(67)  
840(67)  
640(67)  
Mbps  
Mbps  
(66)  
(66)  
(66)  
SERDES factor J  
= 1 to 2, uses  
DDR registers  
Sampling Window  
350  
350  
350  
ps  
Cyclone V Device Datasheet  
48  
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