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5CSEMA5F31C8N 参数 Datasheet PDF下载

5CSEMA5F31C8N图片预览
型号: 5CSEMA5F31C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 85000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 93 页 / 999 K
品牌: INTEL [ INTEL ]
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Cyclone V Device Datasheet  
CV-51002 | 2018.05.07  
6.144-Gbps Support Capability in Cyclone V GT Devices  
Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for  
CPRI 6.144 Gbps.  
Core Performance Specifications  
Clock Tree Specifications  
Table 30.  
Clock Tree Specifications for Cyclone V Devices  
Parameter  
Performance  
–C7, –I7  
550  
Unit  
–C6  
550  
155  
–C8, –A7  
460  
Global clock and Regional clock  
Peripheral clock  
MHz  
MHz  
155  
155  
PLL Specifications  
Table 31.  
PLL Specifications for Cyclone V Devices  
This table lists the Cyclone V PLL block specifications. Cyclone V PLL block does not include HPS PLL.  
Symbol  
Parameter  
Input clock frequency  
Condition  
–C6 speed grade  
–C7, –I7 speed grades  
–C8, –A7 speed grades  
Min  
5
Typ  
Max  
Unit  
MHz  
MHz  
MHz  
MHz  
fIN  
670(52)  
622(52)  
500(52)  
325  
5
5
fINPFD  
Integer input clock frequency to the phase  
frequency detector (PFD)  
5
fFINPFD  
Fractional input clock frequency to the PFD  
50  
160  
MHz  
MHz  
(53)  
fVCO  
PLL voltage-controlled oscillator (VCO)  
operating range  
–C6, –C7, –I7 speed  
grades  
600  
1600  
continued...  
(52)  
This specification is limited in the Intel Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is  
different for each I/O standard.  
Cyclone V Device Datasheet  
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