Cyclone V Device Datasheet
CV-51002 | 2018.05.07
Symbol
Condition
–C6
Typ
—
–C7, –I7
Typ
–C8, –A7
Typ
Unit
Mbps
Mbps
Min
Max
Min
Max
Min
Max
(65)
(66)
(65)
(66)
(65)
(66)
SERDES factor J
= 1 to 2, uses
DDR registers
—
—
(65)
(65)
(65)
(65)
(65)
(65)
Emulated Differential I/O
Standards with Three External
Output Resistor Networks- fHSDR
(data rate)(67)
SERDES factor J
= 4 to 10
—
—
—
640
170
350
—
—
—
640
170
380
—
—
—
550
170
500
Emulated Differential I/O
Standards with One External
Output Resistor Network - fHSDR
(data rate)
SERDES factor J
= 4 to 10
Mbps
ps
tx Jitter -True Differential I/O
Standards(67)
Total Jitterfor
Data Rate, 600
Mbps – 840
Mbps
—
—
—
Total Jitter for
Data Rate <
600Mbps
—
—
—
—
0.21
500
0.15
55
—
—
—
—
0.23
500
0.15
55
—
—
—
—
0.30
500
0.15
55
UI
ps
UI
%
tx Jitter -Emulated Differential I/O
Standards with Three External
Output Resistor Networks
Total Jitter for
Data Rate <
640Mbps
tx Jitter -Emulated Differential I/O
Standards with One External
Output Resistor Network
Total Jitter for
Data Rate <
640Mbps
—
—
—
—
—
—
tDUTY
TX output clock
duty cycle for
both True and
45
50
45
50
45
50
continued...
(66)
(67)
The maximum ideal data rate is the SERDES factor (J) × PLL max output frequency (fout), provided you can close the design timing
and the signal integrity simulation is clean. You can estimate the achievable maximum data rate by performing link timing closure
analysis. You must consider the board skew margin, transmitter delay margin, and receiver sampling margin to determine the
maximum data rate supported.
You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board
skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
Cyclone V Device Datasheet
Send Feedback
47
INTEL [ INTEL ]
