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5CSEMA5F31C8N 参数 Datasheet PDF下载

5CSEMA5F31C8N图片预览
型号: 5CSEMA5F31C8N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 85000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 93 页 / 999 K
品牌: INTEL [ INTEL ]
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Cyclone V Device Datasheet  
CV-51002 | 2018.05.07  
Protocol  
Sub-protocol  
CPRI E12LV  
Data Rate (Mbps)  
1,228.8  
1,228.8  
1,228.8  
2,457.6  
2,457.6  
3,072  
CPRI E12HV  
CPRI E12LVII  
CPRI E24LV  
CPRI E24LVII  
CPRI E30LV  
CPRI E30LVII  
CPRI E48LVII(51)  
CPRI E60LVII(51)  
GbE 1250  
3,072  
4,915.2  
6,144  
Gbps Ethernet (GbE)  
OBSAI  
1,250  
OBSAI 768  
768  
OBSAI 1536  
OBSAI 3072  
SDI 270 SD  
SDI 1485 HD  
SDI 2970 3G  
VbyOne 3750  
HIGIG 3750  
1,536  
3,072  
Serial digital interface (SDI)  
270  
1,485  
2,970  
VbyOne  
HiGig+  
3,750  
3,750  
Related Information  
PCIe Supported Configurations and Placement Guidelines  
Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices  
which require full compliance to the PCIe Gen2 transmit jitter specification.  
(51)  
For CPRI E48LVII and E60LVII, Intel recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full  
compliance to CPRI transmit jitter specification at 4.9152 Gbps (Cyclone V GT and ST devices) and 6.144 Gbps (Cyclone V GT and ST  
devices only). For more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI  
6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.  
Cyclone V Device Datasheet  
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