CV-51002
2015.12.04
43
PLL Specifications
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tDRIFT
Frequency drift after PFDENA is disabled
—
—
—
10
%
for a duration of 100 µs
dKBIT
Bit number of Delta Sigma Modulator
(DSM)
—
8
24
32
Bits
kVALUE
fRES
Numerator of fraction
—
128
8388608
5.96
2147483648
0.023
—
Resolution of VCO frequency
fINPFD = 100 MHz
390625
Hz
Related Information
Memory Output Clock Jitter Specifications on page 50
Provides more information about the external memory interface clock output jitter specifications.
(62)
The cascaded PLL specification is only applicable with the following conditions:
•
•
Upstream PLL: 0.59 MHz ≤ Upstream PLL BW < 1 MHz
Downstream PLL: Downstream PLL BW > 2 MHz
Cyclone V Device Datasheet
Send Feedback
Altera Corporation
INTEL [ INTEL ]
