CV-51002
2015.12.04
41
PLL Specifications
Max Unit
Symbol
Parameter
Condition
Min
Typ
–C6, –C7, –I7 speed
grades
—
—
667(54)
533(54)
55
MHz
MHz
%
Output frequency for external clock
output
fOUT_EXT
–C8, –A7 speed
grades
—
45
—
—
—
—
50
—
—
—
tOUTDUTY
tFCOMP
tDYCONFIGCLK
tLOCK
Duty cycle for external clock output
(when set to 50%)
—
—
—
—
External feedback clock compensation
time
10
ns
Dynamic configuration clock for mgmt_
clk and scanclk
100
1
MHz
ms
Time required to lock from end-of-
device configuration or deassertion of
areset
tDLOCK
Time required to lock dynamically
(after switchover or reconfiguring any
non-post-scale counters/delays)
—
—
—
1
ms
Low
Medium
High(55)
—
—
—
—
—
10
0.3
1.5
4
—
—
—
50
—
MHz
MHz
MHz
ps
fCLBW
PLL closed-loop bandwidth
Accuracy of PLL phase shift
tPLL_PSERR
tARESET
—
—
Minimum pulse width on the areset
—
ns
signal
FREF ≥ 100 MHz
FREF < 100 MHz
—
—
—
—
0.15
750
UI (p-p)
ps (p-p)
(56)(57)
tINCCJ
Input clock cycle-to-cycle jitter
(55)
High bandwidth PLL settings are not supported in external feedback mode.
(56)
A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120
ps.
(57)
FREF is fIN/N, specification applies when N = 1.
Cyclone V Device Datasheet
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