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5CGTFD9E5F31C7N 参数 Datasheet PDF下载

5CGTFD9E5F31C7N图片预览
型号: 5CGTFD9E5F31C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 301000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 95 页 / 1359 K
品牌: INTEL [ INTEL ]
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CV-51002  
2015.12.04  
39  
Core Performance Specifications  
Protocol  
Sub-protocol  
Data Rate (Mbps)  
HiGig+  
HIGIG 3750  
3,750  
Related Information  
PCIe Supported Configurations and Placement Guidelines  
Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices which require full  
compliance to the PCIe Gen2 transmit jitter specification.  
6.144-Gbps Support Capability in Cyclone V GT Devices  
Provides more information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps.  
Core Performance Specifications  
Clock Tree Specifications  
Table 29: Clock Tree Specifications for Cyclone V Devices  
Performance  
–C7, –I7  
550  
Parameter  
Unit  
–C6  
–C8, –A7  
460  
Global clock and Regional clock  
Peripheral clock  
550  
155  
MHz  
MHz  
155  
155  
Cyclone V Device Datasheet  
Send Feedback  
Altera Corporation  
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