CV-51002
2015.12.04
42
PLL Specifications
Symbol
Parameter
Condition
Min
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Typ
—
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Max
Unit
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
FOUT ≥ 100 MHz
FOUT < 100 MHz
300
ps (p-p)
Period jitter for dedicated clock output
in integer PLL
(58)
tOUTPJ_DC
30
mUI (p-p)
ps (p-p)
425(61), 300(59)
42.5(61), 30(59)
Period jitter for dedicated clock output
in fractional PLL
(58)
(58)
tFOUTPJ_DC
mUI (p-p)
ps (p-p)
300
Cycle-to-cycle jitter for dedicated clock
output in integer PLL
tOUTCCJ_DC
30
mUI (p-p)
ps (p-p)
425(61), 300(59)
42.5(61), 30(59)
Cycle-to-cycle jitter for dedicated clock
output in fractional PLL
(58)
tFOUTCCJ_DC
mUI (p-p)
ps (p-p)
650
65
Period jitter for clock output on a
regular I/O in integer PLL
(58)(60)
tOUTPJ_IO
mUI (p-p)
ps (p-p)
650
65
Period jitter for clock output on a
regular I/O in fractional PLL
(58)(60)(61)
tFOUTPJ_IO
mUI (p-p)
ps (p-p)
650
65
Cycle-to-cycle jitter for clock output on
regular I/O in integer PLL
(58)(60)
tOUTCCJ_IO
mUI (p-p)
ps (p-p)
650
65
Cycle-to-cycle jitter for clock output on
regular I/O in fractional PLL
(58)(60)(61)
tFOUTCCJ_IO
mUI (p-p)
ps (p-p)
300
30
Period jitter for dedicated clock output
in cascaded PLLs
(58)(62)
tCASC_OUTPJ_DC
mUI (p-p)
(58)
Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the
intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different
measurement method and are available in Memory Output Clock Jitter Specification for Cyclone V Devices table.
(59)
(60)
This specification only covers fractional PLL for low bandwidth. The fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz.
External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter
Specification for Cyclone V Devices table.
This specification only covers fractional PLL for low bandwidth. The fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz.
(61)
Cyclone V Device Datasheet
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