CV-51002
2015.12.04
45
Periphery Performance
Table 32: Memory Block Performance Specifications for Cyclone V Devices
Resources Used
Performance
–C7, –I7
350
Memory
Mode
Unit
ALUTs
Memory
–C6
420
420
340
–C8, –A7
Single port, all supported widths
0
0
0
1
1
1
300
300
240
MHz
MHz
MHz
Simple dual-port, all supported widths
350
MLAB
Simple dual-port with read and write at
the same address
290
ROM, all supported width
0
0
0
0
1
1
1
1
420
315
315
275
350
275
275
240
300
240
240
180
MHz
MHz
MHz
MHz
Single-port, all supported widths
Simple dual-port, all supported widths
Simple dual-port with the read-during-
write option set to Old Data, all
supported widths
M10K
Block
True dual port, all supported widths
ROM, all supported widths
0
0
1
1
315
315
275
275
240
240
MHz
MHz
Periphery Performance
This section describes the periphery performance, high-speed I/O, and external memory interface.
Actual achievable frequency depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/
IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
Cyclone V Device Datasheet
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