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5CGTFD9E5F31C7N 参数 Datasheet PDF下载

5CGTFD9E5F31C7N图片预览
型号: 5CGTFD9E5F31C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 301000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 95 页 / 1359 K
品牌: INTEL [ INTEL ]
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CV-51002  
2015.12.04  
38  
Transceiver Compliance Specification  
Protocol  
Sub-protocol  
CPRI E6LV  
Data Rate (Mbps)  
614.4  
CPRI E6HV  
CPRI E6LVII  
CPRI E12LV  
CPRI E12HV  
CPRI E12LVII  
CPRI E24LV  
CPRI E24LVII  
CPRI E30LV  
CPRI E30LVII  
CPRI E48LVII(51)  
CPRI E60LVII(51)  
GbE 1250  
614.4  
614.4  
1,228.8  
1,228.8  
1,228.8  
2,457.6  
2,457.6  
3,072  
Common Public Radio Interface (CPRI)  
3,072  
4,915.2  
6,144  
Gbps Ethernet (GbE)  
OBSAI  
1,250  
OBSAI 768  
768  
OBSAI 1536  
OBSAI 3072  
SDI 270 SD  
1,536  
3,072  
270  
Serial digital interface (SDI)  
VbyOne  
SDI 1485 HD  
SDI 2970 3G  
VbyOne 3750  
1,485  
2,970  
3,750  
(51)  
For CPRI E48LVII and E60LVII, Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance  
to CPRI transmit jitter specification at 4.9152 Gbps ( Cyclone V GT and ST devices) and 6.144 Gbps ( Cyclone V GT and ST devices only). For more  
information about the maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver  
Protocol Configurations in Cyclone V Devices chapter.  
Cyclone V Device Datasheet  
Send Feedback  
Altera Corporation  
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