CV-51002
2015.12.04
25
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices
Transceiver Speed Grade 5(30)
Transceiver Speed Grade 6
Transceiver Speed Grade 7
Symbol/Description
Condition
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Spread-spectrum
downspread
PCIe
—
0 to –
0.5%
—
—
0 to –
0.5%
—
—
0 to –
0.5%
—
—
On-chip termina‐
tion resistors
—
—
—
100
—
—
100
—
—
100
—
Ω
VICM (AC coupled)
VCCE_GXBL supply(34)(35)
VCCE_GXBL supply
VCCE_GXBL supply
V
VICM (DC coupled) HCSL I/O standard
for the PCIe
250
—
550
250
—
550
250
—
550
mV
reference clock
10 Hz
—
—
—
—
—
—
—
—
—
—
—
—
—
–50
–80
—
—
—
—
—
—
—
—
—
—
—
—
—
–50
–80
—
—
—
—
—
—
—
—
—
—
—
—
—
–50
–80
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Ω
100 Hz
1 KHz
10 KHz
100 KHz
≥1 MHz
—
–110
–120
–120
–130
—
–110
–120
–120
–130
—
–110
–120
–120
–130
—
Transmitter REFCLK
phase noise(36)
RREF
2000
1%
2000
1%
2000
1%
(30)
Transceiver Speed Grade 5 covers specifications for Cyclone V GT and ST devices.
(34)
Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for Cyclone V GT and ST FPGA systems which
require full compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended
in Cyclone V GT and ST devices under this condition, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
Altera recommends increasing the VCCE_GXBL and VCCL_GXBL typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter
specification at 4.9152 Gbps ( Cyclone V GT and ST devices) and 6.144 Gbps ( Cyclone V GT and ST devices only). For more information about the
maximum full duplex channels recommended in Cyclone V GT and ST devices for CPRI 6.144 Gbps, refer to the Transceiver Protocol
Configurations in Cyclone V Devices chapter.
(35)
(36)
The transmitter REFCLK phase jitter is 30 ps p-p at bit error rate (BER) 10-12
.
Cyclone V Device Datasheet
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