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5CGTFD9E5F31C7N 参数 Datasheet PDF下载

5CGTFD9E5F31C7N图片预览
型号: 5CGTFD9E5F31C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 301000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 95 页 / 1359 K
品牌: INTEL [ INTEL ]
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CV-51002  
2015.12.04  
22  
Differential I/O Standard Specifications  
Differential I/O Standard Specifications  
Table 19: Differential I/O Standard Specifications for Cyclone V Devices  
Differential inputs are powered by VCCPD which requires 2.5 V.  
VCCIO (V)  
VID (mV)(21)  
VICM(DC) (V)  
Condition  
VOD (V)(22)  
Typ  
VOCM (V)(22)(23)  
Min Typ Max  
I/O Standard  
Min  
Typ  
Max  
Min  
Condition  
Max  
Min  
Max  
Min  
Max  
PCML  
Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard. For transmitter, receiver,  
and reference clock I/O pin specifications, refer to Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices table.  
0.05  
1.05  
DMAX  
1.80  
1.55  
700 Mbps  
2.5 V  
VCM  
=
2.375  
2.5  
2.625  
100  
0.247  
0.6  
1.125 1.25  
1.375  
LVDS(24)  
1.25 V  
DMAX  
>
700 Mbps  
BLVDS(25)  
2.375  
2.375  
2.5  
2.5  
2.5  
2.625  
2.625  
2.625  
100  
100  
200  
0.2  
0.6  
0.6  
0.5  
1
1.2  
1.2  
1.4  
1.4  
(26)  
RSDS  
VCM  
=
0.25  
0.300  
1.45  
0.1  
(HIO)(27)  
1.25 V  
Mini-LVDS 2.375  
(HIO)(28)  
600  
1.425 0.25  
(21)  
(22)  
(23)  
(24)  
The minimum VID value is applicable over the entire common mode range, VCM  
RL range: 90 ≤ RL ≤ 110 Ω.  
.
This applies to default pre-emphasis setting only.  
For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rate above 700 Mbps and 0.00 V to  
1.85 V for data rate below 700 Mbps.  
(25)  
(26)  
There are no fixed VICM, VOD, and VOCM specifications for BLVDS. They depend on the system topology.  
For more information about BLVDS interface support in Altera devices, refer to AN522: Implementing Bus LVDS Interface in Supported Altera  
Device Families.  
(27)  
(28)  
For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V.  
For optimized mini-LVDS receiver performance, the receiver voltage input range must be within 0.300 V to 1.425 V.  
Cyclone V Device Datasheet  
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Altera Corporation  
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