CV-51002
2015.12.04
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Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices
Transceiver Speed Grade 5(30)
Transceiver Speed Grade 6
Transceiver Speed Grade 7
Symbol/Description
Condition
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Maximum peak-to-
peak differential
input voltage VID
(diff p-p) after
—
—
—
2.2
—
—
2.2
—
—
2.2
V
device configuration
Minimum differen‐
tial eye opening at
the receiver serial
input pins(40)
—
110
—
—
110
—
—
110
—
—
mV
85-Ω setting
100-Ω setting
120-Ω setting
150-Ω setting
—
—
—
—
85
—
—
—
—
—
—
—
—
85
—
—
—
—
—
—
—
—
85
—
—
—
—
Ω
Ω
Ω
Ω
V
100
120
150
100
120
150
100
120
150
Differential on-chip
termination resistors
2.5 V PCML,
LVPECL, and
LVDS
VCCE_GXBL supply(34)(35)
VCCE_GXBL supply
VCCE_GXBL supply
VICM (AC coupled)
1.5 V PCML
0.65(41)/0.8
V
µs
µs
µs
(42)
tLTR
—
—
—
—
—
—
—
—
—
10
4
—
—
—
—
—
—
10
4
—
—
—
—
—
—
10
4
(43)
tLTD
(44)
tLTD_manual
4
4
4
(40)
The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you enable
the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.
The AC coupled VICM is 650 mV for PCIe mode only.
tLTR is the time required for the receive clock data recovery (CDR) to lock to the input reference clock frequency after coming out of reset.
tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high.
tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodata signal goes high when the CDR is
functioning in the manual mode.
(41)
(42)
(43)
(44)
Cyclone V Device Datasheet
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