CV-51002
2015.12.04
26
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices
Table 21: Transceiver Clocks Specifications for Cyclone V GX, GT, SX, and ST Devices
Transceiver Speed Grade 5(30)
Transceiver Speed Grade 6
Transceiver Speed Grade 7
Symbol/Description
Condition
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fixedclk clock
PCIe Receiver
Detect
—
125
—
—
125
—
—
125
—
MHz
frequency
Transceiver Reconfi‐
guration Controller
IP (mgmt_clk_clk)
clock frequency
—
75
—
100/
75
—
100/
75
—
100/
MHz
125(37)
125(37)
125(37)
Table 22: Receiver Specifications for Cyclone V GX, GT, SX, and ST Devices
Transceiver Speed Grade 5(30)
Transceiver Speed Grade 6
Min Typ Max
Transceiver Speed Grade 7
Symbol/Description
Condition
Unit
Min
Typ
Max
Min
Typ
Max
Supported I/O
standards
1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
Data rate(38)
—
—
—
—
614
—
—
—
—
—
5000/
614
—
—
—
—
—
3125
1.2
—
614
—
—
—
—
—
2500
1.2
—
Mbps
V
6144(35)
Absolute VMAX for a
receiver pin(39)
1.2
—
Absolute VMIN for a
receiver pin
–0.4
—
–0.4
—
–0.4
—
V
Maximum peak-to-
peak differential
1.6
1.6
1.6
V
input voltage VID
(diff p-p) before
device configuration
(37)
The maximum supported clock frequency is 100 MHz if the PCIe hard IP block is enabled or 125 MHz if the PCIe hard IP block is not enabled.
To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
The device cannot tolerate prolonged operation at this absolute maximum.
(38)
(39)
Cyclone V Device Datasheet
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