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5CGTFD9E5F31C7N 参数 Datasheet PDF下载

5CGTFD9E5F31C7N图片预览
型号: 5CGTFD9E5F31C7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 301000-Cell, CMOS, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 95 页 / 1359 K
品牌: INTEL [ INTEL ]
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CV-51002  
2015.12.04  
23  
Switching Characteristics  
VOCM (V)(22)(23)  
VCCIO (V)  
Typ  
VID (mV)(21)  
Condition  
VICM(DC) (V)  
Condition  
VOD (V)(22)  
Typ  
I/O Standard  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Max  
Min  
Typ  
Max  
0.60  
DMAX  
1.80  
700 Mbps  
LVPECL(29)  
SLVS  
300  
1.00  
0.05  
0.05  
0.05  
DMAX  
>
1.60  
1.80  
1.80  
1.80  
700 Mbps  
2.375  
2.5  
2.5  
2.5  
2.625  
2.625  
2.625  
100  
100  
100  
VCM  
=
1.25 V  
Sub-LVDS 2.375  
HiSpi 2.375  
VCM  
=
1.25 V  
VCM  
=
1.25 V  
Related Information  
AN522: Implementing Bus LVDS Interface in Supported Altera Device Families  
Provides more information about BLVDS interface support in Altera devices.  
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices on page 24  
Provides the specifications for transmitter, receiver, and reference clock I/O pin.  
Switching Characteristics  
This section provides performance characteristics of Cyclone V core and periphery blocks.  
(21)  
The minimum VID value is applicable over the entire common mode range, VCM  
RL range: 90 ≤ RL ≤ 110 Ω.  
.
(22)  
(23)  
(29)  
This applies to default pre-emphasis setting only.  
For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rate above 700 Mbps and 0.45  
V to 1.95 V for data rate below 700 Mbps.  
Cyclone V Device Datasheet  
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Altera Corporation  
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