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Switching Characteristics
Table 43 lists the RGMII RX timing characteristics for Cyclone V devices.
Table 43. RGMII RX Timing Requirements for Cyclone V Devices
Symbol Description
Min
—
—
—
1
Typ
Unit
ns
T
clk (1000Base-T)
Tclk (100Base-T)
Tclk (10Base-T)
Tsu
RX_CLK clock period
RX_CLK clock period
RX_CLK clock period
8
40
ns
400
—
ns
RX_D/RX_CTL setup time
ns
Figure 10 shows the timing diagram for RGMII RX timing characteristics.
Figure 10. RGMII RX Timing Diagram
RX_CLK
Tsu
RX_D[3:0]
RX_CTL
Table 44 lists the management data input/output (MDIO) timing characteristics for
Cyclone V devices.
Table 44. MDIO Timing Requirements for Cyclone V Devices
Symbol Description
Min
—
10
10
0
Typ
400
—
Unit
ns
Tclk
Td
Ts
MDC clock period
MDC to MDIO output data delay
Setup time for MDIO data
Hold time for MDIO data
ns
—
ns
Th
—
ns
Figure 11 shows the timing diagram for MDIO timing characteristics.
Figure 11. MDIO Timing Diagram
MDC
Td
MDIO_OUT
MDIO_IN
Th
Tsu
Cyclone V Device Datasheet
December 2013 Altera Corporation
INTEL [ INTEL ]
