Switching Characteristics
Page 37
Table 38. SPI Master Timing Requirements for Cyclone V Devices
Symbol
Description
Min
—
Max
500
Unit
Maximum data input delay from falling edge of SPI_CLK to
data arrival at SoC. The RX sample delay register can be
programmed to control the capture of input data.
Tdinmax
ns
ns
—
Slave select pulse width (Texas Instruments SSP mode)
—
16.67
Figure 5 shows the timing diagram for SPI master timing characteristics.
Figure 5. SPI Master Timing Diagram
Tdsslst
SPI_SS
Tdssfrst
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
Tdio
SPI_MOSI (scph = 1)
SPI_MISO (scph = 1)
Tdinmax
Tdio
SPI_MOSI (scph = 0)
SPI_MISO (scph = 0)
Tdinmax
Table 39 lists the SPI slave timing characteristics for Cyclone V devices. The setup and
hold times can be used for Texas Instruments SSP mode and National Semiconductor
Microwire mode.
Table 39. SPI Slave Timing Requirements for Cyclone V Devices
Symbol Description
Min
20
5
Max
—
—
—
—
—
6
Unit
ns
ns
ns
ns
ns
ns
ns
Tclk
Ts
CLK clock period
MOSI Setup time
MOSI Hold time
Th
5
Tsuss
Thss
Td
Setup time SPI_SS valid before first clock edge
Hold time SPI_SS valid after last clock edge
Master-in slave-out (MISO) output delay
8
8
—
20
—
Slave select pulse width (Texas Instruments SSP mode)
—
December 2013 Altera Corporation
Cyclone V Device Datasheet
INTEL [ INTEL ]
