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Switching Characteristics
Figure 6 shows the timing diagram for SPI slave timing characteristics.
Figure 6. SPI Slave Timing Diagram
Thss
SPI_SS
Tsuss
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
SPI_MISO (scph = 1)
SPI_MOSI (scph = 1)
Td
Ts
Th
Td
SPI_MISO (scph = 0)
SPI_MOSI (scph = 0)
Ts
Th
SD/MMC Timing Characteristics
Table 40 lists the secure digital (SD)/MultiMediaCard (MMC) timing characteristics
for Cyclone V devices.
Table 40. SD/MMC Timing Requirements for Cyclone V Devices
Symbol
Description
Min
20
Max
—
—
55
6
Unit
ns
SDMMC_CLK_OUT clock period (High speed mode)
SDMMC_CLK_OUT clock period (Default speed mode)
SDMMC_CLK_OUT duty cycle
Tclk
40
ns
Tdutycycle
Td
45
%
SDMMC_CMD/SDMMC_D output delay
—
ns
Maximum input delay from rising edge of SDMMC_CLK to
data arrival at SoC
Tdinmax
—
25
ns
Figure 7 shows the timing diagram for SD/MMC timing characteristics.
Figure 7. SD/MMC Timing Diagram
SDMMC_CLK_OUT
Td
SDMMC_CMD & SDMMC_D (Out)
SDMMC_CMD & SDMMC_D (In)
Command/Data Out
Tdinmax
Command/Data In
Cyclone V Device Datasheet
December 2013 Altera Corporation
INTEL [ INTEL ]
