Page 36
Switching Characteristics
QSPI Timing Characteristics
Table 37 lists the queued serial peripheral interface (QSPI) timing characteristics for
Cyclone V devices.
Table 37. QSPI Timing Requirements for Cyclone V Devices
Symbol Description
Fclk CLK clock frequency
Tdutycycle
Tdssfrst
Min
—
Typ
—
Max
108
55
Unit
MHz
%
QSPI_CLK duty cycle
45
—
1/2 cycle of
QSPI_CLK
Output delay QSPI_SS valid before first clock edge
—
—
ns
Tdsslst
Tdio
Output delay QSPI_SS valid after last clock edge
IO Data output delay
–1
–1
—
—
1
1
ns
ns
Maximum data input delay from falling edge of
QSPI_CLK to data arrival at SoC. The delay field of
the qspiregs.rddatacap register can be
programmed to adjust the capture logic of the
incoming data.
Tdinmax
—
—
—
—
Figure 4 shows the timing diagram for QSPI timing characteristics. This timing
diagram illustrates clock polarity mode 0 and clock phase mode 0.
Figure 4. QSPI Timing Diagram
Tdsslst
QSPI_SS
Tdssfrst
QSPI_CLK
QSPI_DATA
Tdio
Tdinmax
Data Out
Data In
SPI Timing Characteristics
Table 38 lists the serial peripheral interface (SPI) master timing characteristics for
Cyclone V devices. The setup and hold times can be used for Texas Instruments SSP
mode and National Semiconductor Microwire mode.
Table 38. SPI Master Timing Requirements for Cyclone V Devices
Symbol Description
Min
—
45
8
Max
16.67
55
Unit
ns
Tclk
CLK clock period
Tdutycycle
Tdssfrst
Tdsslst
Tdio
SPI_CLK duty cycle
%
Output delay SPI_SS valid before first clock edge
Output delay SPI_SS valid after last clock edge
Master-out slave-in (MOSI) output delay
—
ns
8
—
ns
–1
1
ns
Cyclone V Device Datasheet
December 2013 Altera Corporation
INTEL [ INTEL ]
