Switching Characteristics
Page 43
Figure 14 shows the timing diagram for NAND address latch timing characteristics.
Figure 14. NAND Address Latch Timing Diagram
NAND_CLE
NAND_CE
Tcesu
Tclesu
Twp
Twh
NAND_WE
NAND_ALE
Talesu
Taleh
Tdsu
Tdh
NAND_DQ[7:0]
Address
Figure 15 shows the timing diagram for NAND data write timing characteristics.
Figure 15. NAND Data Write Timing Diagram
NAND_CLE
NAND_CE
Tcleh
Tceh
Twp
NAND_WE
NAND_ALE
Talesu
Tdsu
Tdh
NAND_DQ[7:0]
Din
December 2013 Altera Corporation
Cyclone V Device Datasheet