AV-51002
2015.12.16
1-61
SPI Timing Characteristics
Figure 1-8: Quad SPI Flash Timing Diagram
This timing diagram illustrates clock polarity mode 0 and clock phase mode 0.
Tdsslst
QSPI_SS
SCLK_OUT
QSPI_DATA
Tdssfrst
Tdio
Tdin_start
Data Out
Data In
Tdin_end
Related Information
Quad SPI Flash Controller Chapter, Arria V Hard Processor System Technical Reference Manual
Provides more information about Rdelay.
SPI Timing Characteristics
Table 1-52: SPI Master Timing Requirements for Arria V Devices
The setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.
Symbol
Description
Min
16.67
45
Max
—
55
—
—
1
Unit
ns
Tclk
CLK clock period
Tdutycycle
Tdssfrst
Tdsslst
Tdio
SPI_CLK duty cycle
%
Output delay SPI_SS valid before first clock edge
Output delay SPI_SS valid after last clock edge
Master-out slave-in (MOSI) output delay
8
ns
8
ns
–1
ns
(85)
Rdelay is set by programming the register qspiregs.rddatacap. For the SoC EDS software version 13.1 and later, Altera provides automatic Quad
SPI calibration in the preloader. For more information about Rdelay, refer to the Quad SPI Flash Controller chapter in the Arria V Hard Processor
System Technical Reference Manual.
Arria V GX, GT, SX, and ST Device Datasheet
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