AV-51002
2015.12.16
1-57
Memory Output Clock Jitter Specifications
Memory Output Clock Jitter Specifications
Table 1-45: Memory Output Clock Jitter Specifications for Arria V Devices
The memory output clock jitter measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard.
The memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is applied with bit error rate (BER) 10–12, equivalent to 14 sigma.
Altera recommends using the UniPHY intellectual property (IP) with PHYCLK connections for better jitter performance.
–I3, –C4
–I5, –C5
–C6
Parameter
Clock Network
Symbol
Unit
Min
Max
Min
Max
Min
Max
Clock period jitter
PHYCLK
PHYCLK
tJIT(per)
tJIT(cc)
–41
41
–50
50
–55
55
ps
ps
Cycle-to-cycle period jitter
63
90
94
OCT Calibration Block Specifications
Table 1-46: OCT Calibration Block Specifications for Arria V Devices
Symbol
OCTUSRCLK
TOCTCAL
Description
Min
—
Typ
—
Max
20
Unit
Clock required by OCT calibration blocks
MHz
Number of OCTUSRCLKclock cycles required for RS
—
1000
—
Cycles
OCT/RT OCT calibration
TOCTSHIFT
TRS_RT
Number of OCTUSRCLKclock cycles required for OCT
—
—
32
—
—
Cycles
ns
code to shift out
Time required between the dyn_term_ctrland oe
signal transitions in a bidirectional I/O buffer to
dynamically switch between RS OCT and RT OCT
2.5
Arria V GX, GT, SX, and ST Device Datasheet
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