AV-51002
2015.12.16
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Duty Cycle Distortion (DCD) Specifications
Figure 1-7: Timing Diagram for oe and dyn_term_ctrl Signals
Tristate
TX
Tristate
RX
RX
oe
dyn_term_ctrl
TRS_RT
TRS_RT
Duty Cycle Distortion (DCD) Specifications
Table 1-47: Worst-Case DCD on Arria V I/O Pins
The output DCD cycle only applies to the I/O buffer. It does not cover the system DCD.
–I3, –C4
–C5, –I5
–C6
Symbol
Unit
Min
Max
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
45
55
%
HPS Specifications
This section provides HPS specifications and timing for Arria V devices.
For HPS reset, the minimum reset pulse widths for the HPS cold and warm reset signals (HPS_nRST and HPS_nPOR) are six clock cycles of
HPS_CLK1.
Arria V GX, GT, SX, and ST Device Datasheet
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