AV-51002
2015.12.16
1-60
HPS PLL Input Jitter
HPS PLL Input Jitter
Use the following equation to determine the maximum input jitter (peak-to-peak) the HPS PLLs can tolerate. The divide value (N) is the value
programmed into the denominator field of the VCO register for each PLL. The PLL input reference clock is divided by this value. The range of the
denominator is 1 to 64.
Maximum input jitter = Input clock period × Divide value (N) × 0.02
Table 1-50: Examples of Maximum Input Jitter
Input Reference Clock Period
Divide Value (N)
Maximum Jitter
Unit
ns
40 ns
40 ns
40 ns
1
2
4
0.8
1.6
3.2
ns
ns
Quad SPI Flash Timing Characteristics
Table 1-51: Quad Serial Peripheral Interface (SPI) Flash Timing Requirements for Arria V Devices
Symbol
Description
Min
—
Typ
—
Max
108
—
Unit
MHz
ns
Fclk
SCLK_OUT clock frequency (External clock)
Tqspi_clk
QSPI_CLK clock period (Internal reference
clock)
2.32
—
Tdutycycle
Tdssfrst
SCLK_OUT duty cycle
45
—
—
55
—
%
Output delay QSPI_SS valid before first clock
edge
1/2 cycle of
SCLK_OUT
ns
Tdsslst
Output delay QSPI_SS valid after last clock
edge
–1
—
1
1
ns
Tdio
I/O data output delay
Input data valid start
–1
—
—
—
ns
ns
Tdin_start
(2 + Rdelay) ×
Tqspi_clk – 7.52 (85)
Tdin_end
Input data valid end
(2 + Rdelay) ×
—
—
ns
Tqspi_clk – 1.21 (85)
Arria V GX, GT, SX, and ST Device Datasheet
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