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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
1-63  
SPI Timing Characteristics  
Symbol  
Description  
Min  
5
Max  
6
Unit  
ns  
Th  
MOSI Hold time  
Tsuss  
Thss  
Td  
Setup time SPI_SS valid before first clock edge  
Hold time SPI_SS valid after last clock edge  
Master-in slave-out (MISO) output delay  
8
ns  
8
ns  
ns  
Figure 1-10: SPI Slave Timing Diagram  
Thss  
SPI_SS  
Tsuss  
SPI_CLK (scpol = 0)  
SPI_CLK (scpol = 1)  
Td  
SPI_MISO (scph = 1)  
SPI_MOSI (scph = 1)  
Ts  
Th  
Td  
SPI_MISO (scph = 0)  
SPI_MOSI (scph = 0)  
Ts  
Th  
Arria V GX, GT, SX, and ST Device Datasheet  
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Altera Corporation  
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