AV-51002
2015.12.16
1-63
SPI Timing Characteristics
Symbol
Description
Min
5
Max
—
—
—
6
Unit
ns
Th
MOSI Hold time
Tsuss
Thss
Td
Setup time SPI_SS valid before first clock edge
Hold time SPI_SS valid after last clock edge
Master-in slave-out (MISO) output delay
8
ns
8
ns
—
ns
Figure 1-10: SPI Slave Timing Diagram
Thss
SPI_SS
Tsuss
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
Td
SPI_MISO (scph = 1)
SPI_MOSI (scph = 1)
Ts
Th
Td
SPI_MISO (scph = 0)
SPI_MOSI (scph = 0)
Ts
Th
Arria V GX, GT, SX, and ST Device Datasheet
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