AV-51002
2015.12.16
1-62
SPI Timing Characteristics
Symbol
Description
Min
Max
Unit
Tdinmax
Maximum data input delay from falling edge of SPI_CLK to data
arrival at SoC. The RX sample delay register can be programmed to
control the capture of input data.
—
500
ns
Figure 1-9: SPI Master Timing Diagram
Tdsslst
SPI_SS
Tdssfrst
SPI_CLK (scpol = 0)
SPI_CLK (scpol = 1)
Tdio
SPI_MOSI (scph = 1)
SPI_MISO (scph = 1)
Tdinmax
Tdio
SPI_MOSI (scph = 0)
SPI_MISO (scph = 0)
Tdinmax
Table 1-53: SPI Slave Timing Requirements for Arria V Devices
The setup and hold times can be used for Texas Instruments SSP mode and National Semiconductor Microwire mode.
Symbol
Description
Min
20
5
Max
—
Unit
ns
Tclk
Ts
CLK clock period
MOSI Setup time
—
ns
Arria V GX, GT, SX, and ST Device Datasheet
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