AV-51002
2015.12.16
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HPS Clock Performance
HPS Clock Performance
Table 1-48: HPS Clock Performance for Arria V Devices
Symbol/Description
mpu_base_clk (microprocessor unit clock)
main_base_clk (L3/L4 interconnect clock)
h2f_user0_clk
–I3
–C4
925
400
100
100
200
–C5, –I5
800
–C6
700
350
100
100
160
Unit
1050
400
100
100
200
MHz
MHz
MHz
MHz
MHz
400
100
h2f_user1_clk
100
h2f_user2_clk
200
HPS PLL Specifications
HPS PLL VCO Frequency Range
Table 1-49: HPS PLL VCO Frequency Range for Arria V Devices
Description
Speed Grade
–C5, –I5, –C6
–C4
Minimum
320
Maximum
1,600
Unit
MHz
MHz
MHz
VCO range
320
1,850
–I3
320
2,100
HPS PLL Input Clock Range
The HPS PLL input clock range is 10 – 50 MHz. This clock range applies to both HPS_CLK1 and HPS_CLK2 inputs.
Related Information
Clock Select, Booting and Configuration chapter
Provides more information about the clock range for different values of clock select (CSEL).
Arria V GX, GT, SX, and ST Device Datasheet
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