AV-51002
2015.12.16
2-54
Memory Output Clock Jitter Specifications
Memory Output Clock Jitter Specifications
Table 2-50: Memory Output Clock Jitter Specification for Arria V GZ Devices
The clock jitter specification applies to the memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a PLL
output routed on a PHY, regional, or global clock network as specified. Altera recommends using PHY clock networks whenever possible.
The clock jitter specification applies to the memory output clock pins clocked by an integer PLL.
The memory output clock jitter is applicable when an input jitter of 30 ps peak-to-peak is applied with bit error rate (BER) -12, equivalent to 14 sigma.
C3, I3L
C4, I4
Clock Network
Parameter
Symbol
Unit
Min
–55
Max
55
Min
–55
Max
55
Clock period jitter
tJIT(per)
tJIT(cc)
ps
ps
ps
ps
ps
ps
ps
ps
ps
Regional
Cycle-to-cycle period jitter
Duty cycle jitter
–110
–82.5
–82.5
–165
–90
110
82.5
82.5
165
90
–110
–82.5
–82.5
–165
–90
110
82.5
82.5
165
90
tJIT(duty)
tJIT(per)
tJIT(cc)
Clock period jitter
Global
Cycle-to-cycle period jitter
Duty cycle jitter
tJIT(duty)
tJIT(per)
tJIT(cc)
Clock period jitter
–30
30
–35
35
PHY Clock
Cycle-to-cycle period jitter
Duty cycle jitter
–60
60
–70
70
tJIT(duty)
–45
45
–56
56
OCT Calibration Block Specifications
Table 2-51: OCT Calibration Block Specifications for Arria V GZ Devices
Symbol
OCTUSRCLK
TOCTCAL
Description
Min
—
Typ
Max
20
Unit
Clock required by the OCT calibration blocks
—
MHz
Number of OCTUSRCLK clock cycles required for OCT RS/RT calibration
—
1000
—
Cycles
Arria V GZ Device Datasheet
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