AV-51002
2015.12.16
2-30
ATX PLL
ATX PLL
Table 2-27: ATX PLL Specifications for Arria V GZ Devices
Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade.
Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about
device ordering codes, refer to the Arria V Device Overview.
Transceiver Speed Grade 2
Transceiver Speed Grade 3
Symbol/Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
VCO post-divider
L = 2
8000
—
12500
8000
—
10312.5
Mbps
Supported data range
L = 4
L = 8 (154)
—
4000
1000
1
—
—
—
—
6600
3300
—
4000
1000
1
—
—
—
—
6600
3300
—
Mbps
Mbps
µs
(155)
tpll_powerdown
(156)
tpll_lock
—
—
10
—
10
µs
Related Information
•
•
•
Arria V Device Overview
For more information about device ordering codes.
Transceiver Clocking in Arria V Devices
For more information about clocking ATX PLLs.
Dynamic Reconfiguration in Arria V Devices
For more information about reconfiguring ATX PLLs.
(154)
This clock can be further divided by central or local clock dividers making it possible to use ATX PLL for data rates < 1 Gbps. For more information
about ATX PLLs, refer to the Transceiver Clocking in Arria V Devices chapter and the Dynamic Reconfiguration in Arria V Devices chapter.
tpll_powerdown is the PLL powerdown minimum pulse width.
(155)
(156)
tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset.
Arria V GZ Device Datasheet
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