AV-51002
2015.12.16
2-32
Clock Network Data Rate
Clock Network Data Rate
Table 2-29: Clock Network Maximum Data Rate Transmitter Specifications
Valid data rates below the maximum specified in this table depend on the reference clock frequency and the PLL counter settings. Check the MegaWizard
message during the PHY IP instantiation.
ATX PLL
CMU PLL (160)
fPLL
Clock Network
Non-bonded
Mode (Gbps) Mode (Gbps)
Bonded
Channel
Span
Non-bonded
Mode (Gbps) Mode (Gbps)
Bonded
Channel
Span
Non-bonded
Mode (Gbps) Mode (Gbps)
Bonded
Channel
Span
x1 (161)
x6 (161)
x6 PLL Feedback (162)
12.5
—
—
6
6
12.5
—
—
6
6
3.125
—
—
3
12.5
12.5
8.0
12.5
12.5
5.0
3.125
—
6
—
Side-wide
8
—
Side-wide
8
—
—
—
xN (PCIe)
—
—
—
—
8.0
8.0
Up to 13
channels
above and
below PLL
Up to 13
channels
above
and
below
PLL
Up to 13
channels
above and
below PLL
—
8.01 to
9.8304
Up to 7
channels
above
and
below
PLL
xN (Native PHY IP)
7.99
7.99
3.125
3.125
(160)
(161)
(162)
ATX PLL is recommended at 8 Gbps and above data rates for improved jitter performance.
Channel span is within a transceiver bank.
Side-wide channel bonding is allowed up to the maximum supported by the PHY IP.
Arria V GZ Device Datasheet
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