AV-51002
2015.12.16
2-31
Fractional PLL
Fractional PLL
Table 2-28: Fractional PLL Specifications for Arria V GZ Devices
Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade.
Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about
device ordering codes, refer to the Arria V Device Overview.
Transceiver Speed Grade 2
Transceiver Speed Grade 3
Symbol/Description
Conditions
Unit
Min
Typ
Max
Min
Typ
Max
Supported data range
—
600
—
3250/
600
—
3250/
Mbps
3125(157)
3125 (157)
(158)
tpll_powerdown
—
—
1
—
—
—
10
1
—
—
—
10
µs
µs
(159)
tpll_lock
—
Related Information
Arria V Device Overview
For more information about device ordering codes.
(157)
(158)
(159)
When you use fPLL as a TXPLL of the transceiver.
tpll_powerdown is the PLL powerdown minimum pulse width.
tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset.
Arria V GZ Device Datasheet
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