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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
2-29  
CMU PLL  
CMU PLL  
Table 2-26: CMU PLL Specifications for Arria V GZ Devices  
Speed grades shown refer to the PMA Speed Grade in the device ordering code. The maximum data rate could be restricted by the Core/PCS speed grade.  
Contact your Altera Sales Representative for the maximum data rate specifications in each speed grade combination offered. For more information about  
device ordering codes, refer to the Arria V Device Overview.  
Transceiver Speed Grade 2  
Transceiver Speed Grade 3  
Symbol/Description  
Conditions  
Unit  
Min  
600  
1
Typ  
Max  
12500  
Min  
600  
1
Typ  
Max  
10312.5  
Supported data range  
Mbps  
µs  
(152)  
tpll_powerdown  
(153)  
tpll_lock  
10  
10  
µs  
Related Information  
Arria V Device Overview  
For more information about device ordering codes.  
(152)  
(153)  
tpll_powerdown is the PLL powerdown minimum pulse width.  
tpll_lock is the time required for the transmitter CMU/ATX PLL to lock to the input reference clock frequency after coming out of reset.  
Arria V GZ Device Datasheet  
Send Feedback  
Altera Corporation  
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