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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
2-26  
Receiver  
Transceiver Speed Grade 2  
Transceiver Speed Grade 3  
Symbol/Description  
Conditions  
Unit  
Min  
Typ  
Max  
Min  
Typ  
Max  
VCCR_GXB = 0.85 V  
full bandwidth  
600  
600  
mV  
VCCR_GXB = 0.85 V  
half bandwidth  
600  
700  
700  
600  
700  
700  
mV  
mV  
mV  
VICM (AC and DC coupled)  
VCCR_GXB = 1.0 V  
full bandwidth  
VCCR_GXB = 1.0 V  
half bandwidth  
(148)  
tLTR  
4
10  
16  
4
10  
16  
µs  
µs  
µs  
µs  
dB  
(149)  
tLTD  
(150)  
tLTD_manual  
4
4
(151)  
tLTR_LTD_manual  
15  
15  
Programmable equalization  
(AC Gain)  
Full bandwidth (6.25 GHz)  
Half bandwidth (3.125 GHz)  
(148)  
tLTR is the time required for the receive CDR to lock to the input reference clock frequency after coming out of reset.  
(149)  
(150)  
tLTD is time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high.  
tLTD_manual is the time required for the receiver CDR to start recovering valid data after the rx_is_lockedtodatasignal goes high when the CDR is  
functioning in the manual mode.  
tLTR_LTD_manual is the time the receiver CDR must be kept in lock to reference (LTR) mode after the rx_is_lockedtorefsignal goes high when the  
CDR is functioning in the manual mode.  
(151)  
Arria V GZ Device Datasheet  
Send Feedback  
Altera Corporation  
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