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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
2-33  
Standard PCS Data Rate  
Standard PCS Data Rate  
Table 2-30: Standard PCS Approximate Maximum Date Rate (Gbps) for Arria V GZ Devices  
The maximum data rate is also constrained by the transceiver speed grade. Refer to the “Commercial and Industrial Speed Grade Offering for Arria V GZ  
Devices” table for the transceiver speed grade.  
PMA Width  
20  
20  
20  
9
16  
16  
10  
10  
8
8
Transceiver  
Speed Grade  
Mode (163)  
PCS/Core Width  
40  
32  
16  
20  
10  
16  
8
2
3
2
3
C3, I3L  
core speed grade  
9.9  
7.84  
7.2  
5.3  
4.7  
4.24  
3.76  
FIFO  
C4, I4  
core speed grade  
8.8  
9.9  
8.8  
8.2  
9
7.2  
6.56  
7.2  
4.8  
4.9  
4.4  
4.3  
4.,5  
4.1  
3.84  
3.92  
3.52  
3.44  
3.6  
C3, I3L  
core speed grade  
7.92  
7.04  
Register  
C4, I4  
core speed grade  
8.2  
6.56  
3.28  
Related Information  
Operating Conditions on page 2-1  
(163)  
The Phase Compensation FIFO can be configured in FIFO mode or register mode. In the FIFO mode, the pointers are not fixed, and the latency can  
vary. In the register mode the pointers are fixed for low latency.  
Arria V GZ Device Datasheet  
Send Feedback  
Altera Corporation  
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