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5AGXMA1D6F27C6N 参数 Datasheet PDF下载

5AGXMA1D6F27C6N图片预览
型号: 5AGXMA1D6F27C6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 500MHz, 75000-Cell, CMOS, PBGA672, ROHS COMPLIANT, FBGA-672]
分类和应用: 可编程逻辑
文件页数/大小: 182 页 / 2239 K
品牌: INTEL [ INTEL ]
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AV-51002  
2015.12.16  
2-25  
Receiver  
Transceiver Speed Grade 2  
Transceiver Speed Grade 3  
Symbol/Description  
Conditions  
Unit  
Min  
600  
Typ  
Max  
12500  
1.2  
Min  
600  
Typ  
Max  
(143)  
Data rate (10G PCS) (142)  
,
10312.5  
1.2  
Mbps  
V
Absolute VMAX for a receiver pin (144)  
Absolute VMIN for a receiver pin  
–0.4  
–0.4  
V
Maximum peak-to-peak differential  
input voltage VID (diff p-p) before  
device configuration  
1.6  
1.6  
V
VCCR_GXB = 1.0 V  
(VICM = 0.75 V)  
85  
1.8  
2.4  
85  
1.8  
2.4  
V
V
Maximum peak-to-peak differential  
input voltage VID (diff p-p) after  
device configuration (145)  
VCCR_GXB = 0.85 V  
(VICM = 0.6 V)  
Minimum differential eye opening at  
receiver serial input pins (146)(147)  
mV  
Ω
85−Ω setting  
100−Ω setting  
120−Ω setting  
150−Ω setting  
85 30%  
85  
30%  
100  
30%  
100  
30%  
Ω
Differential on-chip termination  
resistors  
120  
30%  
120  
30%  
Ω
150  
30%  
150  
30%  
Ω
(144)  
The device cannot tolerate prolonged operation at this absolute maximum.  
(145)  
(146)  
The maximum peak to peak differential input voltage VID after device configuration is equal to 4 × (absolute VMAX for receiver pin - VICM).  
The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equaliza‐  
tion, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.  
Minimum eye opening of 85 mV is only for the unstressed input eye condition.  
(147)  
Arria V GZ Device Datasheet  
Send Feedback  
Altera Corporation  
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