AV-51002
2015.12.16
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PLL Specifications
PLL Specifications
Table 1-36: PLL Specifications for Arria V Devices
This table lists the Arria V PLL block specifications. Arria V PLL block does not include HPS PLL.
Symbol
Parameter
Condition
–3 speed grade
–4 speed grade
–5 speed grade
–6 speed grade
—
Min
5
Typ
—
—
—
—
—
Max
800(61)
800(61)
750(61)
625(61)
325
Unit
MHz
MHz
MHz
MHz
MHz
5
fIN
Input clock frequency
5
5
fINPFD
Integer input clock frequency to the
phase frequency detector (PFD)
5
fFINPFD
Fractional input clock frequency to the
PFD
—
50
—
160
MHz
–3 speed grade
–4 speed grade
–5 speed grade
–6 speed grade
—
600
600
600
600
40
—
—
—
—
—
1600
1600
1600
1300
60
MHz
MHz
MHz
MHz
%
PLL voltage-controlled oscillator
(VCO) operating range
(62)
fVCO
tEINDUTY
Input clock or external feedback clock
input duty cycle
(61)
(62)
This specification is limited in the Quartus Prime software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
The VCO frequency reported by the Quartus Prime software takes into consideration the VCO post-scale counter Kvalue. Therefore, if the counter K
has a value of 2, the frequency reported can be lower than the fVCO specification.
Arria V GX, GT, SX, and ST Device Datasheet
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