Switching Characteristics
Page 39
DLL Range, DQS Logic Block, and Memory Output Clock Jitter Specifications
Table 33 lists the DLL frequency range specifications for Arria V devices.
Table 33. DLL Frequency Range Specifications for Arria V Devices
Parameter
–I3, –C4
–I5, –C5
–C6
Unit
DLL operating frequency
range
200 – 667
200 – 667
200 – 667
MHz
Table 34 lists the DQS phase shift error for Arria V devices. This error specification is
the absolute maximum and minimum error.
Table 34. DQS Phase Shift Error Specification for DLL-Delayed Clock (tDQS_PSERR) for Arria V
Devices
Number of DQS Delay
–I3, –C4
–I5, –C5
–C6
Unit
Buffer
2
40
80
80
ps
Table 35 lists the memory output clock jitter specifications for Arria V devices.
The memory output clock jitter measurements are for 200 consecutive clock cycles, as
specified in the JEDEC DDR2/DDR3 SDRAM standard.
The memory output clock jitter is applicable when an input jitter of 30 ps (p-p) is
applied with bit error rate (BER) 10–12, equivalent to 14 sigma.
Altera recommends using the UniPHY intellectual property (IP) with PHYCLK
connections for better jitter performance.
Table 35. Memory Output Clock Jitter Specification for Arria V Devices
–I3, –C4
Clock
–I5, –C5
–C6
Parameter
Symbol
Unit
Network
Min
Max
Min
–50
Max
Min
Max
Clock period jitter
PHYCLK
PHYCLK
tJIT(per)
tJIT(cc)
–41
41
50
–55
55
ps
ps
Cycle-to-cycle period jitter
63
90
94
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
INTEL [ INTEL ]
