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Switching Characteristics
OCT Calibration Block Specifications
Table 36 lists the OCT calibration block specifications for Arria V devices.
Table 36. OCT Calibration Block Specifications for Arria V Devices
Symbol
Description
Min
Typ
Max
Unit
OCTUSRCLK
Clock required by OCT calibration blocks
—
—
20
MHz
Number of OCTUSRCLK clock cycles required for
RS OCT /RT OCT calibration
TOCTCAL
—
—
1000
32
—
—
Cycles
Cycles
Number of OCTUSRCLK clock cycles required for OCT code
to shift out
TOCTSHIFT
Time required between the dyn_term_ctrland oesignal
transitions in a bidirectional I/O buffer to dynamically switch
between RS OCT and RT OCT
TRS_RT
—
2.5
—
ns
Figure 6 shows the TRS_RT for oeand dyn_term_ctrlsignals.
Figure 6. Timing Diagram for oe and dyn_term_ctrl Signals
Tristate
TX
Tristate
RX
RX
oe
dyn_term_ctrl
TRS_RT
TRS_RT
Duty Cycle Distortion (DCD) Specifications
Table 37 lists the worst-case DCD for Arria V devices. The output DCD cycle only
applies to the I/O buffer. It does not cover the system DCD.
Table 37. Worst-Case DCD on Arria V I/O Pins
–I3, –C4
Symbol
–C5,–I5
–C6
Unit
Min
Max
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
45
55
%
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
INTEL [ INTEL ]
