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Switching Characteristics
Table 30. High-Speed I/O Specifications for Arria V Devices (1), (2), (3) (Part 3 of 3)
–I3, –C4
–I5, –C5
Min Typ
–C6
Symbol
Conditions
Unit
Min Typ
Max
Max
Min Typ
Max
Non DPA Mode
Sampling Window
Notes to Table 30:
—
—
—
300
—
—
300
—
—
300
ps
(1) When J = 3 to 10, use the serializer/deserializer (SERDES) block.
(2) When J = 1 or 2, bypass the SERDES block.
(3) For LVDS applications, you must use the PLLs in integer PLL mode.
(4) This applies to DPA and soft-CDR modes only.
(5) This applies to non-DPA mode only.
(6) Clock Boost Factor (W) is the ratio between the input data rate and the input clock rate.
(7) This is achieved by using the LVDS clock network.
(8) The Fmax specification is based on the fast clock used for serial data. The interface Fmax is also dependent on the parallel clock domain which is design dependent
and requires timing analysis.
(9) The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you
use. The I/O differential buffer and input register do not have a minimum toggle rate.
(10) The VCC and VCCP must be on a separate power layer and a maximum load of 5 pF for chip-to-chip interface.
(11) The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and the signal
integrity simulation is clean.
(12) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter
channel-to-channel skew, and receiver sampling margin to determine the leftover timing margin.
(13) This applies to default pre-emphasis and VOD settings only.
(14) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin,
transmitter delay margin, and receiver sampling margin to determine the maximum data rate supported.
Figure 3 shows the DPA lock time specifications with the DPA PLL calibration option
enabled.
Figure 3. DPA Lock Time Specification with DPA PLL Calibration Enabled
rx_reset
DPA Lock Time
rx_dpa_locked
256 data
transitions
96 slow
clock cycles
256 data
transitions
96 slow
clock cycles
256 data
transitions
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
INTEL [ INTEL ]
