Switching Characteristics
Page 41
HPS Specifications
This section provides HPS specifications and timing for Arria V devices.
For HPS reset, the minimum reset pulse widths for the HPS cold and warm reset
signals (HPS_nRST and HPS_nPOR) are six clock cycles of HPS_CLK1.
HPS Clock Performance
Table 38 lists the HPS clock performance for Arria V devices.
Table 38. HPS Clock Performance for Arria V Devices
Symbol/Description
mpu_base_clk (microprocessor unit clock)
main_base_clk (L3/L4 interconnect clock)
h2f_user0_clk
–I3
1050
525
100
100
200
–C4
925
462
100
100
200
–C5, –I5
800
–C6
700
350
100
100
160
Unit
MHz
MHz
MHz
MHz
MHz
400
100
h2f_user1_clk
100
h2f_user2_clk
200
HPS PLL Specifications
HPS PLL VCO Frequency Range
Table 39 lists the HPS PLL VCO frequency range for Arria V devices. This
specification applies to all speed grade.
Table 39. HPS PLL VCO Frequency Range for Arria V Devices
Description
Minimum
Maximum
Unit
VCO range
320
1,600
MHz
HPS PLL Input Clock Range
The HPS PLL input clock range is 10 – 50 MHz.
For more information about the clock range for different values of clock select (CSEL),
refer to the Booting and Configuration chapter.
HPS PLL Input Jitter
Use the following equation to determine the maximum input jitter (peak-to-peak) the
HPS PLLs can tolerate.
Maximum input jitter = Input clock period x Divide value (NR) x 0.02
Table 40 shows the examples of the maximum input jitter calculated with the
equation.
Table 40. Examples of Maximum Input Jitter
Input Reference Clock Period
Divide Value (NR)
Maximum Jitter
Unit
ns
40 ns
40 ns
40 ns
1
2
4
0.8
1.6
3.2
ns
ns
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
INTEL [ INTEL ]
