Switching Characteristics
Page 37
Table 31 lists the DPA lock time specifications for Arria V devices, which are
applicable to both commercial and industrial grades. The DPA lock time is for one
channel. One data transition is defined as a 0-to-1 or 1-to-0 transition.
Table 31. DPA Lock Time Specifications for Arria V Devices
Number of Data
Number of
Transitions in One
Repetition of the
Training Pattern
Maximum Data
Transition
Standard
Training Pattern
Repetitions per 256
(1)
Data Transitions
SPI-4
00000000001111111111
00001111
2
2
4
8
8
128
128
64
640
640
640
640
640
Parallel Rapid I/O
10010000
10101010
32
Miscellaneous
01010101
32
Note to Table 31:
(1) This is the number of repetitions for the stated training pattern to achieve the 256 data transitions.
Figure 4 shows the LVDS soft-clock data recovery (CDR)/DPA sinusoidal jitter
tolerance specification for a data rate equal to 1.25 Gbps.
Figure 4. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for a Data Rate Equal to 1.25 Gbps
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification
25
8.5
0.35
0.1
F3
F2
F1
F4
Jitter Frequency (Hz)
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
INTEL [ INTEL ]
