Switching Characteristics
Page 33
Table 27. DSP Block Performance Specifications for Arria V Devices (Part 2 of 2)
Performance
Mode
Unit
–I3, –C4
–I5, –C5
–C6
Modes using Two DSP Blocks
Complex 18 x 19 multiplication
370
310
220
MHz
Memory Block Specifications
Table 28 lists the Arria V memory block specifications.
To achieve the maximum memory block performance, use a memory block clock that
comes through global clock routing from an on-chip PLL and set to 50% output duty
cycle. Use the Quartus II software to report timing for the memory block clocking
schemes.
When you use the error detection cyclical redundancy check (CRC) feature, there is no
degradation in fMAX
.
Table 28. Memory Block Performance Specifications for Arria V Devices
Resources Used
Performance
Memory
Mode
Unit
ALUTs
Memory
–I3, –C4
500
–I5, –C5
450
–C6
400
400
Single port, all supported widths
0
0
1
1
MHz
MHz
Simple dual-port, all supported widths
500
450
MLAB
Simple dual-port with read and write at the
same address
0
1
400
350
300
MHz
ROM, all supported width
—
0
—
1
500
400
400
450
350
350
400
285
285
MHz
MHz
MHz
Single-port, all supported widths
Simple dual-port, all supported widths
0
1
M10K
Block
Simple dual-port with the read-during-write
option set to Old Data, all supported widths
0
1
315
275
240
MHz
True dual port, all supported widths
ROM, all supported widths
0
0
1
1
400
400
350
350
285
285
MHz
MHz
Temperature Sensing Diode Specifications
Table 29 lists the specifications for the Arria V internal temperature sensing diode.
Table 29. Internal Temperature Sensing Diode Specifications for Arria V Devices
Offset
Temperature
Range
Conversion
Time
Minimum Resolution with no
Missing Codes
Accuracy Calibrated Sampling Rate
Option
Resolution
Frequency:
1 MHz
–40 to 100°C
8°C
No
< 100 ms
8 bits
8 bits
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
INTEL [ INTEL ]
