Page 32
Switching Characteristics
Table 26. PLL Specifications for Arria V Devices (Part 3 of 3)
Symbol
Parameter
Min
Typ
Max
Unit
Cycle-to-cycle jitter for clock output on a regular I/O in
fractional PLL (FOUT ≥ 100 MHz)
—
—
600
ps (p-p)
(6),
tFOUTCCJ_IO
(9), (10)
Cycle-to-cycle jitter for clock output on a regular I/O in
fractional PLL (FOUT < 100 MHz)
—
—
—
—
—
—
—
60
mUI (p-p)
ps (p-p)
mUI (p-p)
%
Period jitter for dedicated clock output in cascaded PLLs
(FOUT ≥ 100 MHz)
175
17.5
tCASC_OUTPJ_DC
(6), (7)
Period jitter for dedicated clock output in cascaded PLLs
(FOUT < 100 MHz)
Frequency drift after PFDENAis disabled for a duration of
100 µs
tDRIFT
—
24
10
32
dKBIT
Bit number of Delta Sigma Modulator (DSM)
Numerator of fraction
8
bits
—
kVALUE
128
8388608 2147483648
5.96 0.023
fRES
Resolution of VCO frequency (fINPFD =100 MHz)
390625
Hz
Notes to Table 26:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(2) The voltage-controlled oscillator (VCO) frequency reported by the Quartus II software takes into consideration the VCO post-scale counter value.
Therefore, if the counter has a value of 2, the frequency reported can be lower than the fVCO specification.
(3) This specification is limited by the lower of the two: I/O fMAX or FOUT of the PLL.
K
K
(4) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
(5) FREF is fIN/N, specification applies when N = 1.
(6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to
the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different
measurement method and are available in Table 35 on page 1–39.
(7) The cascaded PLL specification is only applicable with the following conditions:
a. Upstream PLL: 0.59 MHz ≤Upstream PLL BW < 1 MHz
b. Downstream PLL: Downstream PLL BW > 2 MHz
(8) High bandwidth PLL settings are not supported in external feedback mode.
(9) External memory interface clock output jitter specifications use a different measurement method, which are available in Table 35 on page 1–39.
(10) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.05–0.95 must be ≥ 1000 MHz.
(11) This specification only covered fractional PLL for low bandwidth. The fVCO for fractional value range 0.20–0.80 must be ≥ 1200 MHz.
DSP Block Specifications
Table 27 lists the Arria V DSP block performance specifications.
Table 27. DSP Block Performance Specifications for Arria V Devices (Part 1 of 2)
Performance
Mode
Unit
–I3, –C4
–I5, –C5
–C6
Modes using One DSP Block
Independent 9 x 9 Multiplication
370
370
370
370
310
370
370
310
310
310
310
250
310
310
220
220
220
220
200
220
220
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Independent 18 x 19 Multiplication
Independent 18 x 25 Multiplication
Independent 20 x 24 Multiplication
Independent 27 x 27 Multiplication
Two 18 x 19 Multiplier Adder Mode
18 x 18 Multiplier Added Summed with 36-bit Input
Arria V GX, GT, SX, and ST Device Datasheet
December 2013 Altera Corporation
INTEL [ INTEL ]
