欢迎访问ic37.com |
会员登录 免费注册
发布采购

5AGXFB3K6F31C5N 参数 Datasheet PDF下载

5AGXFB3K6F31C5N图片预览
型号: 5AGXFB3K6F31C5N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 622MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 可编程逻辑
文件页数/大小: 122 页 / 2566 K
品牌: INTEL [ INTEL ]
 浏览型号5AGXFB3K6F31C5N的Datasheet PDF文件第26页浏览型号5AGXFB3K6F31C5N的Datasheet PDF文件第27页浏览型号5AGXFB3K6F31C5N的Datasheet PDF文件第28页浏览型号5AGXFB3K6F31C5N的Datasheet PDF文件第29页浏览型号5AGXFB3K6F31C5N的Datasheet PDF文件第31页浏览型号5AGXFB3K6F31C5N的Datasheet PDF文件第32页浏览型号5AGXFB3K6F31C5N的Datasheet PDF文件第33页浏览型号5AGXFB3K6F31C5N的Datasheet PDF文件第34页  
Page 30  
Switching Characteristics  
Core Performance Specifications  
This section describes the clock tree, phase-locked loop (PLL), digital signal  
processing (DSP), memory blocks and temperature sensing diode specifications.  
Clock Tree Specifications  
Table 25 lists the clock tree specifications for Arria V devices.  
Table 25. Clock Tree Performance for Arria V Devices  
Performance  
Parameter  
–I3, –C4  
Unit  
–I5, –C5  
625  
–C6  
525  
350  
Global clock and Regional clock  
Peripheral clock  
625  
450  
MHz  
MHz  
400  
PLL Specifications  
Table 26 lists the Arria V PLL block specifications. Arria V PLL block does not include  
HPS PLL.  
Table 26. PLL Specifications for Arria V Devices (Part 1 of 3)  
Symbol  
Parameter  
Min  
5
Typ  
Max  
Unit  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
MHz  
%
(1)  
Input clock frequency (–3 speed grade)  
Input clock frequency (–4 speed grade)  
Input clock frequency (–5 speed grade)  
Input clock frequency (–6 speed grade)  
Integer input clock frequency to the PFD  
Fractional input clock frequency to the PFD  
PLL VCO operating range (–3 speed grade)  
PLL VCO operating range (–4 speed grade)  
PLL VCO operating range (–5 speed grade)  
PLL VCO operating range (–6 speed grade)  
Input clock or external feedback clock input duty cycle  
800  
800  
750  
625  
(1)  
(1)  
(1)  
5
fIN  
5
5
fINPFD  
5
325  
fFINPFD  
50  
600  
600  
600  
600  
40  
160  
1600  
1600  
1600  
1300  
60  
(2)  
fVCO  
tEINDUTY  
Output frequency for internal global or regional clock  
(–3 speed grade)  
(3)  
500  
500  
500  
400  
MHz  
MHz  
MHz  
MHz  
Output frequency for internal global or regional clock  
(–4 speed grade)  
(3)  
(3)  
(3)  
fOUT  
Output frequency for internal global or regional clock  
(–5 speed grade)  
Output frequency for internal global or regional clock  
(–6 speed grade)  
(3)  
(3)  
(3)  
(3)  
Output frequency for external clock output (–3 speed grade)  
Output frequency for external clock output (–4 speed grade)  
Output frequency for external clock output (–5 speed grade)  
Output frequency for external clock output (–6 speed grade)  
Duty cycle for external clock output (when set to 50%)  
45  
50  
670  
670  
622  
500  
MHz  
MHz  
MHz  
MHz  
%
fOUT_EXT  
tOUTDUTY  
55  
Arria V GX, GT, SX, and ST Device Datasheet  
December 2013 Altera Corporation  
 复制成功!