Switching Characteristics
Page 31
Table 26. PLL Specifications for Arria V Devices (Part 2 of 3)
Symbol
tFCOMP
tDYCONFIGCLK
Parameter
Min
—
Typ
—
Max
10
Unit
ns
External feedback clock compensation time
Dynamic configuration clock for mgmt_clkand scanclk
—
—
100
MHz
Time required to lock from end-of-device configuration or
deassertion of areset
tLOCK
tDLOCK
—
—
—
—
1
1
ms
ms
Time required to lock dynamically (after switchover or
reconfiguring any non-post-scale counters/delays)
PLL closed-loop low bandwidth
—
—
—
—
10
—
—
0.3
1.5
4
—
—
MHz
MHz
fCLBW
PLL closed-loop medium bandwidth
(8)
PLL closed-loop high bandwidth
—
MHz
tPLL_PSERR
tARESET
Accuracy of PLL phase shift
—
—
—
—
50
ps
Minimum pulse width on the aresetsignal
Input clock cycle-to-cycle jitter (FREF ≥ 100 MHz)
Input clock cycle-to-cycle jitter (FREF < 100 MHz)
—
ns
0.15
750
UI (p-p)
ps (p-p)
(4), (5)
tINCCJ
Period jitter for dedicated clock output in integer PLL
(FOUT ≥ 100 MHz)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
175
ps (p-p)
mUI (p-p)
ps (p-p)
(6)
tOUTPJ_DC
Period jitter for dedicated clock output in integer PLL
(FOUT < 100 MHz)
17.5
Period jitter for dedicated clock output in fractional PLL
(FOUT ≥ 100 MHz)
250 (10)
,
175 (11)
(6)
tFOUTPJ_DC
tOUTCCJ_DC
tFOUTCCJ_DC
Period jitter for dedicated clock output in fractional PLL
(FOUT < 100 MHz)
25 (10)
,
mUI (p-p)
ps (p-p)
17.5 (11)
Cycle-to-cycle jitter for dedicated clock output in integer
PLL (FOUT ≥ 100 MHz)
175
(6)
Cycle-to-cycle jitter for dedicated clock output in integer
PLL (FOUT < 100 MHz)
17.5
mUI (p-p)
ps (p-p)
Cycle-to-cycle jitter for dedicated clock output in fractional
PLL (FOUT ≥ 100 MHz)
250 (10)
175 (11)
,
(6)
Cycle-to-cycle jitter for dedicated clock output in fractional
PLL (FOUT < 100 MHz)
25 (10)
,
mUI (p-p)
ps (p-p)
17.5 (11)
Period jitter for clock output on a regular I/O in integer PLL
(FOUT ≥ 100 MHz)
600
(6),
tOUTPJ_IO
(9)
Period jitter for clock output on a regular I/O in integer PLL
(FOUT < 100 MHz)
60
600
60
mUI (p-p)
ps (p-p)
Period jitter for clock output on a regular I/O in fractional
PLL (FOUT ≥ 100 MHz)
(6),
tFOUTPJ_IO
(9), (10)
Period jitter for clock output on a regular I/O in fractional
PLL (FOUT < 100 MHz)
mUI (p-p)
ps (p-p)
Cycle-to-cycle jitter for clock output on a regular I/O in
integer PLL (FOUT ≥ 100 MHz)
600
60
(6),
tOUTCCJ_IO
(9)
Cycle-to-cycle jitter for clock output on a regular I/O in
integer PLL (FOUT < 100 MHz)
mUI (p-p)
December 2013 Altera Corporation
Arria V GX, GT, SX, and ST Device Datasheet
INTEL [ INTEL ]
