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326769-002 参数 Datasheet PDF下载

326769-002图片预览
型号: 326769-002
PDF下载: 下载PDF文件 查看货源
内容描述: 移动第三代英特尔®科雷亚?? ¢处理器家族 [Mobile 3rd Generation Intel® Core™ Processor Family]
分类和应用:
文件页数/大小: 342 页 / 2513 K
品牌: INTEL [ INTEL ]
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Processor Configuration Registers  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/1/0–2/PCI  
4–5h  
0000h  
RO, RW  
16 bits  
00h  
Size:  
BIOS Optimal Default  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
Memory Access Enable (MAE)  
0 = All of device's memory space is disabled.  
1
RW  
0b  
0b  
Uncore  
Uncore  
1 = Enable the Memory and Pre-fetchable memory address  
ranges defined in the MBASE, MLIMIT, PMBASE, and  
PMLIMIT registers.  
IO Access Enable (IOAE)  
0 = All of device’s I/O space is disabled.  
1 = Enable the I/O address range defined in the IOBASE, and  
IOLIMIT registers.  
0
RW  
2.6.4  
PCISTS—PCI Status Register  
This register reports the occurrence of error conditions associated with primary side of  
the "virtual" Host-PCI Express* bridge embedded within the Root port.  
B/D/F/Type:  
Address Offset:  
Reset Value:  
Access:  
0/1/0–2/PCI  
6–7h  
0010h  
RO, RW1C, RO-V  
16 bits  
Size:  
BIOS Optimal Default  
0h  
Reset  
Value  
RST/  
PWR  
Bit  
Access  
Description  
Detected Parity Error (DPE)  
This bit is set by a Function whenever it receives a Poisoned TLP,  
regardless of the state the Parity Error Response bit in the  
Command register. On a Function with a Type 1 Configuration  
header, the bit is set when the Poisoned TLP is received by its  
Primary Side.  
15  
RW1C  
0b  
Uncore  
Reset Value of this bit is 0b.  
This bit will be set only for completions of requests encountering  
ECC error in DRAM.  
Poisoned peer-to-peer posted forwarded will not set this bit. They  
are reported at the receiving port.  
Signaled System Error (SSE)  
This bit is set when this Device sends an SERR due to detecting  
an ERR_FATAL or ERR_NONFATAL condition and the SERR Enable  
bit in the Command register is '1'. Both received (if enabled by  
BCTRL1[1]) and internally detected error messages do not affect  
this field.  
14  
13  
RW1C  
0b  
0b  
Uncore  
Uncore  
Received Master Abort Status (RMAS)  
This bit is set when a Requester receives a Completion with  
Unsupported Request Completion Status. On a Function with a  
Type 1 Configuration header, the bit is set when the Unsupported  
Request is received by its Primary Side.  
RO  
Not applicable. UR not on primary interface.  
90  
Datasheet, Volume 2